S/X-Band Multi-Channel Receiver Units (MRUs)

As the number of Receive and Transmit channels are increasing day by day, due to the requirement of Digital Beam Forming (DBF) in the Radars form sub-array level DBF to element level DBF. In future, the number of receive channels will become equals to the number of antenna elements. Existing technology using super heterodyne receiver with one/two stages down converter followed by digital down converter implemented inside FPGA cannot meet the SWaP-CR requirements. Use of Xilinx RFSoC with inbuilt multi-channel RFADC and RFDAC is one of the promising technology to mitigate the challenges.

Based on availability of Gen3 RFSoC devices, two numbers of S-Band MRU is planned to be developed as Design Verification Model (DVM) along with a Test Jig consisting of external synchronizer to prove multi-board synchronization. Based on the availability of newer devices in future which can support up to X-band signal generation and X-Band direct RF sampling, development of X-Band MRU DVMs will be taken up.

The S-band and X-band architecture of MRUs will be similar except the clocking scheme and the front end receiver ahead of the RF ADC. The main function the Multi-Channel Receiver Unit (MRU) are reception of eight channels of S-band RF signals and carries out low noise amplification and filtering, reception of dwell parameters from external subsystem over 10G Ethernet on multimode fiber or Gigabit Ethernet on copper, sampling of RF signals, performing Digital Down Conversion to create Baseband I/Q data, multiplexing eight channel baseband data, sending to external subsystem over 10G Ethernet on multimode fiber. It is also responsible for synthesis of RF signals using Digital Up Conversion of baseband signals and RF DACs. The baseband signals are stored as I/Q data in internal memory. It receives master clock references over optical/RF lines, critical timings over LVDS, synchronizes with other MRUs, and provides sampling clocks to ADCs and DACs, clock to FPGA.